1. Field of the Invention
The invention relates to reference buffer circuits, and in particular, to an enhanced reference buffer circuit structure capable of providing reference voltages with a large range.
2. Description of the Related Art
In analog circuit applications, particularly for analog to digital converters (ADCs) such as pipeline ADC, Flash ADC, and SAR ADC, a reference buffer circuit with sufficient driving capability is an essential component to provide accurate reference voltages. As the technology advances, the supply power for circuit design is required to be lower than ever, therefore it is getting challenging to implement a reference buffer circuit with low supply power while its driving capability remains sustainable.
FIG. 1 shows a conventional reference buffer circuit 100. The reference buffer circuit 100 mainly comprises a buffering stage 110 and a driving stage 120 both driven by a supply voltage VDD. The buffering stage 110 provides a high driving voltage VGH and a low driving voltage VGL respectively based on a high input voltage VinH and a low input voltage VinL, and the driving stage is driven by the high driving voltage VGH and the low driving voltage VGL to output a high output voltage VoutH and a low output voltage VoutL. Specifically, the buffering stage 110 comprises a first NMOS transistor M1 with its drain coupled to the supply voltage VDD, and a first PMOS transistor M2 with its drain connected to a signal ground. A first operational amplifier OP1 has two input ends and one output end. The first input end receives the high input voltage VinH, the second input end is connected to the source of the first NMOS transistor M1, and an output end is coupled to the gate of the first NMOS transistor M1 to provide the high driving voltage VGH. The second operational amplifier OP2 has the same deployment. The first input end of the second operational amplifier OP2 receives the low input voltage VinL, the second input end is connected to the source of the first PMOS transistor M2, and the output end coupled to the gate of the first PMOS transistor M2 provides the low driving voltage VGL. Optionally, at least one buffering stage resistor RB is coupled between the sources of the first NMOS transistor M1 and first PMOS transistor M2 to generate a voltage drop. By applying the high input voltage VinH to the first operational amplifier OP1, the first operational amplifier OP1 locks the gate voltage of first NMOS transistor M1 at the high driving voltage VGH. Likewise, the second operational amplifier OP2 is controlled by the low input voltage VinL to lock the gate voltage of first PMOS transistor M2 at the low driving voltage VGL. Thereby, the driving stage 120 is driven by the high driving voltage VGH and low driving voltage VGL to accurately output the high output voltage VoutH and low output voltage VoutL.
Specifically, the driving stage 120 comprises two MOSFETs and a resistor. The second NMOS transistor M3 has a drain for receiving the supply voltage VDD, a gate for receiving the high driving voltage VGH, and a source for outputting the high output voltage VoutH. Symmetrically, the second PMOS transistor M4 has a drain coupled to the signal ground, a gate coupled to the low driving voltage VGL, and a source for outputting the low output voltage VoutL. At least one driving stage resistor RD may be put between the sources of the second NMOS transistor M3 and second PMOS transistor M4. The driving stage 120 is also referred to as a replica circuit, in which the high output voltage VoutH and low output voltage VoutL are used as reference voltages that can possess high driving capabilities.
In order to enlarge the dynamic range of the reference voltage to meet the system requirement, the low output voltage VoutL is required to be reduced; however, due to the circuit characteristic of the reference buffer circuit 100, the low output voltage VoutL can not be lower than the gate-to-source voltage of the second PMOS transistor M4. In other words, the low output voltage VoutL is lower bounded. Likewise, the high output voltage VoutH is upper bounded. These physical limitations have constraint the dynamic range that a reference voltage generator can provide. Since a further dynamic range is required, an enhanced circuit structure to overcome the issue is also desirable.